Stay Ahead, Stay ONMINE

The $400 million machine powering the future of chipmaking

Jos Benschop is climbing a ladder to get to the top of his newest machine.  It’s a bit of a schlep. The contraption is the size of a double-decker bus—more than 150 tons of gleaming precision-milled aluminum covered in thousands of snaking tubes, colored cables, and pressurized tanks. From the ground, it looks like a futuristic V8 engine. When I reach the top with Benschop we’re looking down from about 15 feet in the air, with bunny-suited technicians scurrying around below. It’s more than 200 cubic meters of tech—“mechatronic devices that hold a few mirrors in a position with atomic precision,” he says, gesturing at the gargantuan apparatus. Benschop, a tall and grizzled 66-year-old, has spent over a decade working with his engineers to design this thing, but even so, he’ll sometimes look at it and go: Oh my God. Benschop is the executive vice president of technology for ASML, a Dutch company that is the linchpin of the microchip industry. If you want to make powerful chips to power phones or AI, a lithography machine like the one we’re standing on is what you need to create increasingly tiny circuitry. Lithography is the art and science of shining light on a silicon wafer to pattern out the transistors, wiring, and other components of the microchips that will be cut from it. The chipmaking field is essentially controlled by only two big players: ASML, which creates the lithography machines, and TSMC, the chipmaking giant. Nine years ago, ASML began selling machines that use a daring new way of patterning chip features. These machines employ extreme-ultraviolet light, or EUV—radiation well outside the visible spectrum that they produce by shooting lasers at tiny molten drops of tin, tens of thousands of times a second. Those first machines—the result of an R&D moonshot that lasted 16 years and cost about $10 billion—can craft transistor features with a resolution of 13 nanometers. This new machine can do even better: It has a resolution of just eight nanometers, the width of about 40 silicon atoms. The devices are now shipping to chipmaking factories, or fabs, at an eye-watering price: $400 million each. But chipmakers will fork that cash over, because they are in a desperate race to produce new and improved chips every year. That means getting their mitts on machines that can make ever smaller components and cram them together ever more densely—part of a long-standing recipe for creating faster and more energy-­efficient chips.  For years now, ASML’s tools have been critical to keeping Moore’s Law alive. Without the company’s advanced chipmaking technology it is very possible that chip density—and the ability to perform ever more calculations—would have plateaued.  The AI industry has produced new and ravenous demand for denser chips, as firms like OpenAI and Anthropic scramble to erect server farms that train and deploy new, ever-more-powerful models, which require new, ever-more-powerful hardware. ASML’s latest machine promises to help keep the AI party raging for at least another decade.  “We can allow customers to go to smaller and smaller features, and that opens up the space for whatever we see now today in AI, which is absolutely mind-blowing,” Marco Pieters, ASML’s CTO, told me. “I think we’ve only seen the tip of the iceberg.”  Its relentless push for “shrink”—as they call it in the chipmaking industry—has made ASML a dominant force: The company produces about 90% of all chip-­lithography tools worldwide. If you make chips, ASML is unavoidable. But that monopoly position makes some people, and governments, uneasy. The chipmaking field is essentially controlled by only two big players: ASML, which creates the lithography machines, and TSMC, the chipmaking giant in Taiwan, which uses ASML’s machines to craft the vast majority of all microchips. This duopoly is so powerful that it has geopolitical implications. In an effort to prevent China from developing advanced AI, the US government pressured the Dutch government to impose an embargo in 2019: ASML isn’t allowed to sell high-end machines to any Chinese firm. Geopolitically, “chips are the new oil,” says Marc Hijink, the author of Focus: The ASML Way. Being deprived of them can be as disastrous as being deprived of oil. And in that metaphor, you might say, ASML is the Strait of Hormuz. James Proud, the cofounder and CEO of the lithography startup Substrate, says the situation is not ideal. The US is “dangerously reliant” on a supply chain that’s overseas and increasingly pricey, Substrate says on its website. “There’s a huge concentration in a small number of players,” Proud says. “And the supply chain is just very expensive.”  Which is why, after two decades of ASML’s dominance, would-be competitors are now gunning for its territory. China is hungrily pouring billions into trying to replicate ASML’s tech. And startups like Substrate are trying to get in the game as well, setting their sights on creating lithography machines that are cheaper, smaller, and even more capable than ASML’s behemoths. Will any of them succeed? The near future clearly belongs to ASML, but as its engineers well know, you can unseat a giant with the right trick of the light. Making chips is, oddly, a bit like silk-screening a T-shirt. To print a pattern on a silicon wafer, you start with a pattern on a reticle—a mask that carries the design. Shining a light on the reticle transfers that pattern to the wafer. The light interacts with a layer of chemicals on the wafer, fixing the pattern in place.  The size of a chip’s features is partly set by the wavelength of light the machine uses: The smaller the wavelength, the teensier the circuitry you can create. You can stretch the capabilities of a wavelength somewhat; increasing what’s known as the numerical aperture, which usually means swapping in a bigger lens, can further focus the light and thus lay down patterns for smaller and smaller components. Eventually, though, this trick hits its limit, and you need to find a new form of light with a smaller wavelength.  So the history of chipmaking has been a two-step dance. The industry finds a good source of light, eventually increases the numerical aperture, and then finally accepts the need for a smaller wavelength, starting the two-step all over again. Up to the early 1990s, chipmakers used visible light, with a wavelength of about 400 nanometers. By the mid-’90s they’d upgraded to deep ultraviolet, ultimately getting it down to a 193-nanometer wavelength. By the late ’90s they saw the end of the line approaching for deep ultraviolet. But what would come next? All the options were troublesome. They could shift to x-rays, with a teensy one-­nanometer wavelength, but they were devilishly hard to focus. Beams of electrons and ions were equally precise; but they worked like dot-matrix printers, transferring a pattern point by point, which was far too slow. (The chip industry wants a machine to crank out hundreds of wafers per hour.)  “It’s a very engineering-heavy company: Let’s send thousands of engineers and just have them mow down these problems. That’s what they did, and it worked.” Jeff Koch, analyst, SemiAnalysis Around 2001, ASML, then a smaller player in the lithography world, placed its bet on another option: EUV, with a wavelength just shy of the x-ray range. Nikon and Canon were working on it as well, but they dropped out—while ASML kept going. The idea was full of unknowns. Nobody knew how to reliably generate that type of light, nor how to focus it; EUV is absorbed by regular glass lenses. It’s even absorbed by air. ASML figured it would take six full years to wade through this R&D nightmare.  In reality it took those 16 years and about $10 billion in research, but it worked. The machine, which works in a vacuum, creates EUV light by vaporizing molten tin and using mirrors to direct it. Zeiss, a historic German optics company, had to invent new techniques for polishing and inspecting the mirrors, using an ion beam to knock off minute imperfections.  “They sort of ignored the buzz of, like, Hey, this is never gonna work, and they just beat their heads against these huge engineering problems,” says Jeff Koch, who used to work for ASML and is now an analyst for the chip-industry research firm SemiAnalysis. “It’s a very engineering-­heavy company: Let’s send thousands of engineers and just have them mow down these problems. That’s what they did, and it worked.”  When the first EUV machines went on the market in 2017, they cost well over $100 million apiece. Some observers wondered whether the demand would really be there from the major chipmaking firms—TSMC, Samsung, and Intel. In the years chipmakers were waiting for EUV to happen, the lithography industry had developed clever ways to improve on old-fashioned deep ultraviolet light. (If you put a layer of water on top of the wafer, for example, the light could focus more narrowly.) Maybe EUV wouldn’t be much needed for a while? But ASML lucked out. Only a few years after EUV debuted, OpenAI released GPT-3 and then ChatGPT. Artificial intelligence burst into the mainstream. Instantly, firms like OpenAI, Google, Meta, and Anthropic were hungry for increasingly high-end chips as they built massive server farms to train and deploy large language models. EUV made it easier and faster to crank out AI-tailored chip designs. Nvidia began producing elite GPUs—processors perfectly suited for AI training—that cost $40,000 a pop; the big companies couldn’t get enough. The AI wars were on, and EUV was in demand. In 2025, ASML says, it sold nearly 50 EUV machines to companies and pulled in nearly $40 billion in revenue. As of press time, the company’s market cap was over half a trillion dollars.  ASML’s new machines have no shortage of potential customers. But there is one in particular, with deep pockets, that can’t buy them for any amount of money: China.  The US wants to hobble China’s ability to create cutting-edge AI chips—or any advanced chips, for that matter. So when ASML began selling its original EUV machines, in 2017, the Trump administration successfully pressured the Dutch government to forbid the company from selling them to any Chinese firms. The US had also imposed export controls on China’s telecom giant Huawei, banning US firms from using its 4G and 5G equipment. This one-two punch incensed the Chinese government and stirred it to action. China is now pouring billions into catching up and trying to develop its own EUV chip-patterning technology. A Reuters report last winter found that a government skunkworks employing former ASML staffers had cobbled together a machine so huge it filled the entire floor of a lab. It’s unclear how well it works. The experiment may well be making some chips, says Hijink, but he doubts it can do so at an industrial scale. A mirror is installed in an optical system for the high-NA machine.COURTESY OF ZEISS Officially, the government denied it was pushing to develop EUV tech. An editorial in the Global Times—a newspaper closely allied with the Chinese government—pooh-poohed the report, claiming that China was still happy to work with the West to get access to chips. “Our goal has never been to build a self-­sufficient ‘technology island’ in isolation,” it stated, “but rather, on the basis of achieving autonomy and control over key technologies, to integrate more deeply and equally into the global innovation network.” Experts say the reality is in the middle. China definitely craves a domestic ability to make high-end chips. And unlike ASML, it doesn’t need its EUV machinery to be efficient and profitable, cranking out about 200 wafers an hour. Any output would help wean it off reliance on the West.  “They would be very happy to have a tool that does one wafer per hour and it costs them a fortune to run,” Koch says. “They would build a fab with a thousand of those and be super happy with it.”  Still, producing and managing EUV light well is a feat that might take years, some told me. In the meantime, the Chinese will lean hard on deep-ultraviolet lithography, developed in the ’90s, making the most of an alternative but slower approach known as multi-­patterning, says David Lin, senior advisor for tech leadership at the Special Competitive Studies Project, a think tank that focuses on security and technology. “They’re going to push DUV to the absolute limits,” Lin says. The AI race is also pushing China to devise ever cleverer ways of developing LLMs that don’t rely on the fastest AI chips. In the US, OpenAI, Anthropic, and Google are fighting over who can buy the biggest piles of hot Nvidia chips. Since China can’t compete that way, it is innovating not in hardware but in software—building lighter-­weight LLMs like DeepSeek.  As China rumbles into action, ASML has remained laser focused on shrink. To go even smaller, Benschop and his engineers decided, they wouldn’t shift to a new form of light. They’d do the second part of the two-step: They’d raise the numerical aperture of the machine by more than half (for those keeping track of the specific numbers, it would be a switch from an NA of 0.33 to an NA of 0.55). That would let them cut the size of the transistors by close to half and nearly triple their density on a chip.  This would also be an easier climb. Without the need to develop an entirely new source of light, the new machine—based on high-numerical-aperture EUV, or “high NA”—would be evolutionary, not revolutionary. Still, building the new system did present a few gnarly challenges. In an EUV machine, the way you transfer an image onto a wafer is by shining light at the microchip pattern on the reticle and then using an optical system to take the reflected light and demagnify that pattern, shrinking it down to the size you want on the wafer. The light hits only part of the reticle at any given time, so you quickly move the reticle back and forth to expose every part of the pattern to the light. Going to a higher numerical aperture meant they could have smaller features on the reticle. But this also meant that some of the light would be arriving at the reticle—and reflecting off it—at a steeper angle.  That’s what caused problems. The pattern on the reticle is three-dimensional, so light arriving at such a steep angle caused shadows—much the way slanted sunlight creates shadows in the Grand Canyon. That stood to diminish the machine’s ability to make clear patterns. The new reticle moves with acceleration up to 22 g, much faster than in the company’s original EUV machine. “Don’t try to sit on it, because you’ll pass out.” The solution was to change the pattern on the reticle—along with the way the mirrors took the light and shrank it down to impart the pattern to the wafer. The designs on the reticle would now be twice as long as they were wide—stretched, as it were, in one dimension. But this design came with its own problems. The changes to the mirrors meant the area on the wafer exposed during a single scan was half the size it was with the original EUV machines, reducing the system’s speed. And ASML couldn’t tolerate any slowdown: Chipmakers were paying it for machines with massive throughput, about 200 wafers an hour. If one part of the system slowed down, another part would have to speed up. The engineers decided the machine should move the reticle faster, which meant making the entire mechanism lighter and dramatically redesigning it. The new reticle moves with acceleration up to 22 g, much faster than in the company’s original EUV machine. “Don’t try to sit on it, because you’ll pass out,” Pieters told me. The wafer stage moves around faster as well, in tandem with the reticle. Meanwhile, over in Germany, Zeiss’s engineers were busy designing mirrors to accommodate the higher numerical aperture and asymmetric shaping of the light. The new mirrors would be about twice as large as those in the regular EUV machines, and the projection system, which carries light from the reticle to the wafer, weighed fully 12 tons, seven times more than before. Zeiss built a new robot-assisted production line to handle these ponderous new beasts. The company says they’re the smoothest surfaces they’ve ever made.  At the same time, ASML was working on making its EUV light source even more powerful, to help make the wafer-exposing process go faster. The engineers calculated that they could improve the output of EUV if they hit each tin droplet three times with the laser instead of twice, as they do in the first machine. That meant the already-hectic system of firing tin would need to speed up by 50%. “The lasers just keep getting bigger,” says Alex Schafgans, the head of engineering at ASML in San Diego, where the EUV light source is built.  Indeed, the lasers for a single machine now fill an entire room. After Benschop showed me the massive high-NA device, we walked across the hall and entered a chamber filled with hulking six-foot-tall boxes that were part of the laser system. Peering through tiny windows in the sides of the units, we could see the glowing purple plasma used in creating the laser light. When high-NA machines began to roll off the assembly line, one company was waiting hungrily: Intel. The company purchased the very first high-NA machine put up for sale, and in the spring of 2024, 300 ASML engineers showed up in Oregon at one of Intel’s fabs to begin assembling and testing it.  “ASML actually put a giant ribbon around one of the boxes,” says Mark Phillips, an Intel fellow who is director of its hardware and lithography solutions, laughing. His team has been testing the machine to see how well it performs; Phillips wouldn’t give details other than to say he’s “very pleased at the rapid pace of tool health.” He also wouldn’t give a date for when Intel would start using it to make chips, though observers say that will likely happen next year. The company plans to ease it in, using it for just a few precision components on a chip and then gradually for more and more.  What’s at stake is a chance to recapture its mojo. Intel was once a silicon powerhouse, designing the most cutting-edge CPUs for computers and servers, and building them in its own fabs. But in the 2010s, the big new markets were mobile-phone chips and GPUs for AI and gaming, and Intel rapidly lost ground. Apple designed its own mobile chips (and had TSMC make them), while Nvidia did the same thing with GPUs. Google began banging out its own TSMC-made AI chips called TPUs in 2015, and soon it was stuffing data centers full of them. Intel fellow Mark Phillips briefs members of the media on the high-NA tool at the company’s Fab D1X in Hillsboro, Oregon. Intel was ASML’s first customer for the new EUV machine.COURTESY OF INTEL CORPORATION So in 2021 Intel announced a moonshot. It would aggressively begin building out a foundry business, one that would go toe to toe with TSMC. Instead of creating Intel chips, the Intel foundry would manufacture designs for customers like makers of mobile phones and AI chips.  Intel hopes that being the first to wield high-NA technology will give it an edge in the silicon rat race, making it possible to print tiny patterns faster than anyone else.  It could also make things simpler for customers. Over the years, while waiting for EUV machines to emerge, chip designers used multi-patterning to squeeze more life out of the older forms of light. Every chip is made out of layers, which are laid down to make components like the switches and wiring. If you’re working on one of those layers and need to make features tinier than your machine can normally produce, you can break the pattern for that layer up into several patterns and then expose the wafer to them one at a time. This strategy helped chipmakers keep using older (and cheaper) machines while still creating tinier and tinier components. But multi-patterning is a hassle: It’s more challenging to design the complex overlay of patterns, and much slower to print each chip. Designing a chip is far easier if you know you can do “single patterning,” blasting each layer in one go.  Observers say it won’t be easy to build a foundry business that bests TSMC and Samsung on their own terrain. “Leapfrogging is difficult,” Hijink says. But it’s also true that the high-tech world has such a ravening hunger for better chips that Intel could succeed, simply because even TSMC and Samsung can’t fulfill all that need.  “There’s spillover demand, so Intel can survive off that,” Koch says. “It’s not even scraps now. It’s a meal. It may not be the best foundry, but they can make chips, and there’s only three companies that can do that, right?” TSMC, for its part, seems to be biding its time when it comes to high NA. “TSMC will deploy high-NA EUV when it is mature and ready to deliver maximum benefit to our customers,” the company wrote to MIT Technology Review. Some suspect it won’t use the machines in serious volume until the 2030s. Part of the reason is cost: TSMC is ruthlessly focused on producing chips as cost-effectively as possible, and the high-NA tools are a blistering $400 million each, far more than the previous EUV rigs. And unlike those, the new machines are not a revolutionary leap upward.  “This is like 30% to 50% better in terms of capability,” says Koch, the analyst and former ASML employee. “This is probably the first tool that hasn’t obviously made business sense right away for ASML.” It’s not that the industry won’t eventually embrace high NA en masse, Koch says. Most companies will need to, if they want to keep going smaller. But TSMC is more likely to push ahead as far as it can go with its existing EUV tools, using onerous multi-patterning to wring as much as it can out of that generation until it absolutely needs to switch.  “The industry has only shifted paradigms when it just absolutely cannot extend—even one more little bit—out of what it’s been doing,” Koch says.  China isn’t the only party looking to upset the current balance of power. The dominance of ASML, and the swelling cost of its tools, is prompting other upstarts too. But instead of trying to replicate ASML’s breakthroughs in EUV, they’re doing an end run—working on lithography tools that use entirely different forms of light. These will be far cheaper, they promise, and just as powerful. One is Substrate, a San Francisco–based startup. Founded four years ago, it’s working on a tool that uses x-ray light produced by a particle accelerator. X-rays have a remarkably tiny wavelength, making them a potentially powerful way to create minute features.  Particle accelerators have historically been enormous, making them difficult to fit into a chipmaking process. Substrate says it has harnessed decades of scientific improvements in particle acceleration to produce a light source that’s smaller and suitable for mass production.  Last year the company released images showing that it had created fine patterns, which Proud, the CEO, says are only possible now with a high-NA EUV machine. He says Substrate’s goal is to produce chips at scale by 2030.  But Proud doesn’t intend to sell the tools to TSMC or Intel. Indeed, he doesn’t plan to sell them to anyone. Instead, Substrate wants to create its own fab, building chips using its own tools.   “The amount of chips we’re going to need is going to be many orders of magnitude larger than even the wildest projections you have now.” James Proud, cofounder and CEO, Substrate The semiconductor industry, Proud argues, needs new approaches, because it’s become too pricey and too centralized. A single fab today can cost $25 billion to build, up from about $5 billion in the 2010s, the company notes. It’s driving the cost of a single wafer full of advanced chips up toward $100,000, Proud says.  “That is, I think, a prohibitive cost,” he says. There also isn’t enough capacity in the supply chain: “It’s relatively slow and hard to flex to the current increase in demands.” He admires ASML’s EUV tooling—it’s “the apex implementation of that technology”—but new approaches are needed. That’s partly for national security reasons. Proud and his team think it’s too dangerous for the US to rely on foreign supplies. But he also predicts the current AI boom will go into overdrive, creating a massive demand for chips that the existing ASML/TSMC duopoly won’t be able to deliver: “The amount of chips we’re going to need is going to be many orders of magnitude larger than even the wildest projections you have now.” ASML’s machines use lasers and molten tin to generate the EUV light.CHRISTOPHER PAYNE Substrate predicts it will be able to produce finished wafers at $10,000 a pop—a tenth of where Proud predicts the rest of the industry is heading. Proud says that’s partly because the company’s system will be vertically integrated, so it will control all parts of the chipmaking process, but also because its lithography tooling will be less complex: “We’re able to put together in a sort of simpler package.” Still, Substrate is playing its cards close to its chest. Unlike ASML, the company isn’t offering nuanced detail on how it generates light, or on how that then translates into making patterns on a wafer.  Substrate’s ambitions give some industry observers pause. Hijink, who thinks it is probably “unachievable and impossible” to simultaneously master both a new form of lithography and high-throughput fab techniques, regards the company’s secrecy as a red flag. “This industry is about open innovation,” he says. Koch is more impressed by its ambitions and funding. The type of technology it’s pursuing “is really cool,” he says. “It’s interesting.” But “there’s a long road between lab-scale demonstration and high volume,” he adds. “Is this like an imminent disruption to ASML? Probably not.”   Another startup that is aiming to hit the market around the same time as Substrate is Lace Lithography. Based in Norway, it is devising an entirely different approach—one that doesn’t use light at all. Instead, an energized beam of helium atoms is pointed at the pattern on the reticle. When the helium atoms then hit the wafer, the atoms transfer their energy to it, imparting the design to the chip.  The idea dates back a while. Bodil Holst, the CEO, took it up in 2008, when she was a physicist studying the use of atom beams. MIT professor Henry “Hank” Smith, a pioneer in using x-rays for lithography, told her she should explore using atoms as a mechanism for making microchips, because back then he wasn’t sure ASML’s EUV moonshot would work. “Even if it does, we’ll need atoms eventually,” he told her. Holst did some experiments to investigate the idea further and partnered with a former PhD student—Adrià Salvador Palau, a physicist and expert in machine learning—to found Lace. Like Substrate’s, its tool is completely different from ASML’s massive machinery. The source of the excited atoms “looks a bit like a rocket motor,” says Palau. “It’s very cool.” While EUV’s wavelength is 13.5 nanometers, the helium atoms offer a precision of 0.1 nanometers. The process also requires far less power, and the machine is intended to be far smaller. Holst tells me the company aims to have machines ready to sell to fabs by 2029 or 2030. “I think everybody’s really looking forward to something that extends a road map beyond light, beyond EUV,” Palau says.  ASML is watching these upstarts with curiosity. Benschop says he can’t assess whether Substrate’s technology will work reliably and affordably, because the company hasn’t explained anything about its processes. But he went to a conference where Holst and Palau did a presentation outlining Lace Lithography’s technology. “I’m incredibly impressed with how they do it,” he says. The problem, he says, is he doesn’t think the process produces patterns on the wafer that are deep enough to be useful. “I cannot see how they would scale it to a viable volume product,” he told me.  He suspects ASML’s mastery of EUV will keep it on top for the near future. “So far, I have not seen a viable alternative,” he says. He thinks there’s “no serious runner-up” when it comes to volume manufacturing of the most advanced chip generations. It’s true that major shifts in chipmaking are slow, says Chris Miller, a professor of international history at Tufts University and the author of Chip War, a book about the worldwide struggle for dominance in the industry. “No doubt we’ll eventually have alternatives [to EUV],” he told me via e-mail. “But it’s worth noting that lithography transitions have historically taken years, if not decades.”  ASML’s executives, too, are pondering their future. Benschop expects high-NA technology to dominate chipmaking into the 2030s. Beyond that? The industry has, indeed, tended to shift to a new form of light every decade. “You may argue it’s time for the next decade,” he told me after we’d stripped off our bunny suits and he was relaxing with a coffee.  But ASML’s executives suspect they can continue to squeeze more capabilities out of EUV by increasing the numerical aperture even further on their existing machine. They’re already toying with a design that would take an NA of 0.55 to an NA of 0.75: “hyper NA.” It could let them pattern wafers with a resolution of six nanometers. They’re also working on standardizing their various optics into a platform of a single size, so customers could order one machine outfitted for either regular EUV, high NA, or hyper NA. If it’s all in the same-sized unit, it would simplify the costs and logistics of integrating each into a fab. If the company goes through with it, Benschop figures, the hyper-NA tool might hit the market seven or eight years from now and be sold in volume during the second half of the 2030s. For now, the ball is in ASML’s court. “We’re pushing the limits of physics,” Pieters told me. The question now is whether anyone else can push harder.  Clive Thompson is a science and technology journalist based in New York City. He wrote about the development of ASML’s original EUV machine in MIT Technology Review’s 2021 issue on computing.

Jos Benschop is climbing a ladder to get to the top of his newest machine. 

It’s a bit of a schlep. The contraption is the size of a double-decker bus—more than 150 tons of gleaming precision-milled aluminum covered in thousands of snaking tubes, colored cables, and pressurized tanks. From the ground, it looks like a futuristic V8 engine. When I reach the top with Benschop we’re looking down from about 15 feet in the air, with bunny-suited technicians scurrying around below.

It’s more than 200 cubic meters of tech—“mechatronic devices that hold a few mirrors in a position with atomic precision,” he says, gesturing at the gargantuan apparatus. Benschop, a tall and grizzled 66-year-old, has spent over a decade working with his engineers to design this thing, but even so, he’ll sometimes look at it and go: Oh my God.

Benschop is the executive vice president of technology for ASML, a Dutch company that is the linchpin of the microchip industry. If you want to make powerful chips to power phones or AI, a lithography machine like the one we’re standing on is what you need to create increasingly tiny circuitry. Lithography is the art and science of shining light on a silicon wafer to pattern out the transistors, wiring, and other components of the microchips that will be cut from it.

The chipmaking field is essentially controlled by only two big players: ASML, which creates the lithography machines, and TSMC, the chipmaking giant.

Nine years ago, ASML began selling machines that use a daring new way of patterning chip features. These machines employ extreme-ultraviolet light, or EUV—radiation well outside the visible spectrum that they produce by shooting lasers at tiny molten drops of tin, tens of thousands of times a second. Those first machines—the result of an R&D moonshot that lasted 16 years and cost about $10 billion—can craft transistor features with a resolution of 13 nanometers. This new machine can do even better: It has a resolution of just eight nanometers, the width of about 40 silicon atoms. The devices are now shipping to chipmaking factories, or fabs, at an eye-watering price: $400 million each.

But chipmakers will fork that cash over, because they are in a desperate race to produce new and improved chips every year. That means getting their mitts on machines that can make ever smaller components and cram them together ever more densely—part of a long-standing recipe for creating faster and more energy-­efficient chips. 

For years now, ASML’s tools have been critical to keeping Moore’s Law alive. Without the company’s advanced chipmaking technology it is very possible that chip density—and the ability to perform ever more calculations—would have plateaued. 

The AI industry has produced new and ravenous demand for denser chips, as firms like OpenAI and Anthropic scramble to erect server farms that train and deploy new, ever-more-powerful models, which require new, ever-more-powerful hardware. ASML’s latest machine promises to help keep the AI party raging for at least another decade. 

“We can allow customers to go to smaller and smaller features, and that opens up the space for whatever we see now today in AI, which is absolutely mind-blowing,” Marco Pieters, ASML’s CTO, told me. “I think we’ve only seen the tip of the iceberg.” 

Its relentless push for “shrink”—as they call it in the chipmaking industry—has made ASML a dominant force: The company produces about 90% of all chip-­lithography tools worldwide. If you make chips, ASML is unavoidable.

But that monopoly position makes some people, and governments, uneasy. The chipmaking field is essentially controlled by only two big players: ASML, which creates the lithography machines, and TSMC, the chipmaking giant in Taiwan, which uses ASML’s machines to craft the vast majority of all microchips. This duopoly is so powerful that it has geopolitical implications. In an effort to prevent China from developing advanced AI, the US government pressured the Dutch government to impose an embargo in 2019: ASML isn’t allowed to sell high-end machines to any Chinese firm. Geopolitically, “chips are the new oil,” says Marc Hijink, the author of Focus: The ASML Way. Being deprived of them can be as disastrous as being deprived of oil. And in that metaphor, you might say, ASML is the Strait of Hormuz.

James Proud, the cofounder and CEO of the lithography startup Substrate, says the situation is not ideal. The US is “dangerously reliant” on a supply chain that’s overseas and increasingly pricey, Substrate says on its website. “There’s a huge concentration in a small number of players,” Proud says. “And the supply chain is just very expensive.” 

Which is why, after two decades of ASML’s dominance, would-be competitors are now gunning for its territory. China is hungrily pouring billions into trying to replicate ASML’s tech. And startups like Substrate are trying to get in the game as well, setting their sights on creating lithography machines that are cheaper, smaller, and even more capable than ASML’s behemoths. Will any of them succeed? The near future clearly belongs to ASML, but as its engineers well know, you can unseat a giant with the right trick of the light.


Making chips is, oddly, a bit like silk-screening a T-shirt. To print a pattern on a silicon wafer, you start with a pattern on a reticle—a mask that carries the design. Shining a light on the reticle transfers that pattern to the wafer. The light interacts with a layer of chemicals on the wafer, fixing the pattern in place. 

The size of a chip’s features is partly set by the wavelength of light the machine uses: The smaller the wavelength, the teensier the circuitry you can create. You can stretch the capabilities of a wavelength somewhat; increasing what’s known as the numerical aperture, which usually means swapping in a bigger lens, can further focus the light and thus lay down patterns for smaller and smaller components. Eventually, though, this trick hits its limit, and you need to find a new form of light with a smaller wavelength. 

So the history of chipmaking has been a two-step dance. The industry finds a good source of light, eventually increases the numerical aperture, and then finally accepts the need for a smaller wavelength, starting the two-step all over again. Up to the early 1990s, chipmakers used visible light, with a wavelength of about 400 nanometers. By the mid-’90s they’d upgraded to deep ultraviolet, ultimately getting it down to a 193-nanometer wavelength. By the late ’90s they saw the end of the line approaching for deep ultraviolet. But what would come next?

All the options were troublesome. They could shift to x-rays, with a teensy one-­nanometer wavelength, but they were devilishly hard to focus. Beams of electrons and ions were equally precise; but they worked like dot-matrix printers, transferring a pattern point by point, which was far too slow. (The chip industry wants a machine to crank out hundreds of wafers per hour.) 

“It’s a very engineering-heavy company: Let’s send thousands of engineers and just have them mow down these problems. That’s what they did, and it worked.”

Jeff Koch, analyst, SemiAnalysis

Around 2001, ASML, then a smaller player in the lithography world, placed its bet on another option: EUV, with a wavelength just shy of the x-ray range. Nikon and Canon were working on it as well, but they dropped out—while ASML kept going. The idea was full of unknowns. Nobody knew how to reliably generate that type of light, nor how to focus it; EUV is absorbed by regular glass lenses. It’s even absorbed by air. ASML figured it would take six full years to wade through this R&D nightmare. 

In reality it took those 16 years and about $10 billion in research, but it worked. The machine, which works in a vacuum, creates EUV light by vaporizing molten tin and using mirrors to direct it. Zeiss, a historic German optics company, had to invent new techniques for polishing and inspecting the mirrors, using an ion beam to knock off minute imperfections. 

“They sort of ignored the buzz of, like, Hey, this is never gonna work, and they just beat their heads against these huge engineering problems,” says Jeff Koch, who used to work for ASML and is now an analyst for the chip-industry research firm SemiAnalysis. “It’s a very engineering-­heavy company: Let’s send thousands of engineers and just have them mow down these problems. That’s what they did, and it worked.” 

When the first EUV machines went on the market in 2017, they cost well over $100 million apiece. Some observers wondered whether the demand would really be there from the major chipmaking firms—TSMC, Samsung, and Intel. In the years chipmakers were waiting for EUV to happen, the lithography industry had developed clever ways to improve on old-fashioned deep ultraviolet light. (If you put a layer of water on top of the wafer, for example, the light could focus more narrowly.) Maybe EUV wouldn’t be much needed for a while?

But ASML lucked out. Only a few years after EUV debuted, OpenAI released GPT-3 and then ChatGPT. Artificial intelligence burst into the mainstream. Instantly, firms like OpenAI, Google, Meta, and Anthropic were hungry for increasingly high-end chips as they built massive server farms to train and deploy large language models. EUV made it easier and faster to crank out AI-tailored chip designs. Nvidia began producing elite GPUs—processors perfectly suited for AI training—that cost $40,000 a pop; the big companies couldn’t get enough. The AI wars were on, and EUV was in demand. In 2025, ASML says, it sold nearly 50 EUV machines to companies and pulled in nearly $40 billion in revenue. As of press time, the company’s market cap was over half a trillion dollars. 


ASML’s new machines have no shortage of potential customers. But there is one in particular, with deep pockets, that can’t buy them for any amount of money: China. 

The US wants to hobble China’s ability to create cutting-edge AI chips—or any advanced chips, for that matter. So when ASML began selling its original EUV machines, in 2017, the Trump administration successfully pressured the Dutch government to forbid the company from selling them to any Chinese firms. The US had also imposed export controls on China’s telecom giant Huawei, banning US firms from using its 4G and 5G equipment.

This one-two punch incensed the Chinese government and stirred it to action. China is now pouring billions into catching up and trying to develop its own EUV chip-patterning technology. A Reuters report last winter found that a government skunkworks employing former ASML staffers had cobbled together a machine so huge it filled the entire floor of a lab. It’s unclear how well it works. The experiment may well be making some chips, says Hijink, but he doubts it can do so at an industrial scale.

A mirror is installed in an optical system for the high-NA machine.
COURTESY OF ZEISS

Officially, the government denied it was pushing to develop EUV tech. An editorial in the Global Times—a newspaper closely allied with the Chinese government—pooh-poohed the report, claiming that China was still happy to work with the West to get access to chips. “Our goal has never been to build a self-­sufficient ‘technology island’ in isolation,” it stated, “but rather, on the basis of achieving autonomy and control over key technologies, to integrate more deeply and equally into the global innovation network.”

Experts say the reality is in the middle. China definitely craves a domestic ability to make high-end chips. And unlike ASML, it doesn’t need its EUV machinery to be efficient and profitable, cranking out about 200 wafers an hour. Any output would help wean it off reliance on the West. 

“They would be very happy to have a tool that does one wafer per hour and it costs them a fortune to run,” Koch says. “They would build a fab with a thousand of those and be super happy with it.” 

Still, producing and managing EUV light well is a feat that might take years, some told me. In the meantime, the Chinese will lean hard on deep-ultraviolet lithography, developed in the ’90s, making the most of an alternative but slower approach known as multi-­patterning, says David Lin, senior advisor for tech leadership at the Special Competitive Studies Project, a think tank that focuses on security and technology. “They’re going to push DUV to the absolute limits,” Lin says.

The AI race is also pushing China to devise ever cleverer ways of developing LLMs that don’t rely on the fastest AI chips. In the US, OpenAI, Anthropic, and Google are fighting over who can buy the biggest piles of hot Nvidia chips. Since China can’t compete that way, it is innovating not in hardware but in software—building lighter-­weight LLMs like DeepSeek. 


As China rumbles into action, ASML has remained laser focused on shrink. To go even smaller, Benschop and his engineers decided, they wouldn’t shift to a new form of light. They’d do the second part of the two-step: They’d raise the numerical aperture of the machine by more than half (for those keeping track of the specific numbers, it would be a switch from an NA of 0.33 to an NA of 0.55). That would let them cut the size of the transistors by close to half and nearly triple their density on a chip. 

This would also be an easier climb. Without the need to develop an entirely new source of light, the new machine—based on high-numerical-aperture EUV, or “high NA”—would be evolutionary, not revolutionary.

Still, building the new system did present a few gnarly challenges. In an EUV machine, the way you transfer an image onto a wafer is by shining light at the microchip pattern on the reticle and then using an optical system to take the reflected light and demagnify that pattern, shrinking it down to the size you want on the wafer. The light hits only part of the reticle at any given time, so you quickly move the reticle back and forth to expose every part of the pattern to the light.

Going to a higher numerical aperture meant they could have smaller features on the reticle. But this also meant that some of the light would be arriving at the reticle—and reflecting off it—at a steeper angle. 

That’s what caused problems. The pattern on the reticle is three-dimensional, so light arriving at such a steep angle caused shadows—much the way slanted sunlight creates shadows in the Grand Canyon. That stood to diminish the machine’s ability to make clear patterns.

The new reticle moves with acceleration up to 22 g, much faster than in the company’s original EUV machine. “Don’t try to sit on it, because you’ll pass out.”

The solution was to change the pattern on the reticle—along with the way the mirrors took the light and shrank it down to impart the pattern to the wafer. The designs on the reticle would now be twice as long as they were wide—stretched, as it were, in one dimension.

But this design came with its own problems. The changes to the mirrors meant the area on the wafer exposed during a single scan was half the size it was with the original EUV machines, reducing the system’s speed. And ASML couldn’t tolerate any slowdown: Chipmakers were paying it for machines with massive throughput, about 200 wafers an hour.

If one part of the system slowed down, another part would have to speed up. The engineers decided the machine should move the reticle faster, which meant making the entire mechanism lighter and dramatically redesigning it. The new reticle moves with acceleration up to 22 g, much faster than in the company’s original EUV machine. “Don’t try to sit on it, because you’ll pass out,” Pieters told me. The wafer stage moves around faster as well, in tandem with the reticle.

Meanwhile, over in Germany, Zeiss’s engineers were busy designing mirrors to accommodate the higher numerical aperture and asymmetric shaping of the light. The new mirrors would be about twice as large as those in the regular EUV machines, and the projection system, which carries light from the reticle to the wafer, weighed fully 12 tons, seven times more than before. Zeiss built a new robot-assisted production line to handle these ponderous new beasts. The company says they’re the smoothest surfaces they’ve ever made. 

At the same time, ASML was working on making its EUV light source even more powerful, to help make the wafer-exposing process go faster. The engineers calculated that they could improve the output of EUV if they hit each tin droplet three times with the laser instead of twice, as they do in the first machine. That meant the already-hectic system of firing tin would need to speed up by 50%. “The lasers just keep getting bigger,” says Alex Schafgans, the head of engineering at ASML in San Diego, where the EUV light source is built. 

Indeed, the lasers for a single machine now fill an entire room. After Benschop showed me the massive high-NA device, we walked across the hall and entered a chamber filled with hulking six-foot-tall boxes that were part of the laser system. Peering through tiny windows in the sides of the units, we could see the glowing purple plasma used in creating the laser light.


When high-NA machines began to roll off the assembly line, one company was waiting hungrily: Intel. The company purchased the very first high-NA machine put up for sale, and in the spring of 2024, 300 ASML engineers showed up in Oregon at one of Intel’s fabs to begin assembling and testing it. 

“ASML actually put a giant ribbon around one of the boxes,” says Mark Phillips, an Intel fellow who is director of its hardware and lithography solutions, laughing. His team has been testing the machine to see how well it performs; Phillips wouldn’t give details other than to say he’s “very pleased at the rapid pace of tool health.” He also wouldn’t give a date for when Intel would start using it to make chips, though observers say that will likely happen next year. The company plans to ease it in, using it for just a few precision components on a chip and then gradually for more and more. 

What’s at stake is a chance to recapture its mojo. Intel was once a silicon powerhouse, designing the most cutting-edge CPUs for computers and servers, and building them in its own fabs. But in the 2010s, the big new markets were mobile-phone chips and GPUs for AI and gaming, and Intel rapidly lost ground. Apple designed its own mobile chips (and had TSMC make them), while Nvidia did the same thing with GPUs. Google began banging out its own TSMC-made AI chips called TPUs in 2015, and soon it was stuffing data centers full of them.

over the shoulders of a crowd of workers in cleanroom suits listening to a central figure.
Intel fellow Mark Phillips briefs members of the media on the high-NA tool at the company’s Fab D1X in Hillsboro, Oregon. Intel was ASML’s first customer for the new EUV machine.
COURTESY OF INTEL CORPORATION

So in 2021 Intel announced a moonshot. It would aggressively begin building out a foundry business, one that would go toe to toe with TSMC. Instead of creating Intel chips, the Intel foundry would manufacture designs for customers like makers of mobile phones and AI chips. 

Intel hopes that being the first to wield high-NA technology will give it an edge in the silicon rat race, making it possible to print tiny patterns faster than anyone else. 

It could also make things simpler for customers. Over the years, while waiting for EUV machines to emerge, chip designers used multi-patterning to squeeze more life out of the older forms of light. Every chip is made out of layers, which are laid down to make components like the switches and wiring. If you’re working on one of those layers and need to make features tinier than your machine can normally produce, you can break the pattern for that layer up into several patterns and then expose the wafer to them one at a time. This strategy helped chipmakers keep using older (and cheaper) machines while still creating tinier and tinier components. But multi-patterning is a hassle: It’s more challenging to design the complex overlay of patterns, and much slower to print each chip. Designing a chip is far easier if you know you can do “single patterning,” blasting each layer in one go. 

Observers say it won’t be easy to build a foundry business that bests TSMC and Samsung on their own terrain. “Leapfrogging is difficult,” Hijink says. But it’s also true that the high-tech world has such a ravening hunger for better chips that Intel could succeed, simply because even TSMC and Samsung can’t fulfill all that need. 

“There’s spillover demand, so Intel can survive off that,” Koch says. “It’s not even scraps now. It’s a meal. It may not be the best foundry, but they can make chips, and there’s only three companies that can do that, right?”

TSMC, for its part, seems to be biding its time when it comes to high NA. “TSMC will deploy high-NA EUV when it is mature and ready to deliver maximum benefit to our customers,” the company wrote to MIT Technology Review. Some suspect it won’t use the machines in serious volume until the 2030s. Part of the reason is cost: TSMC is ruthlessly focused on producing chips as cost-effectively as possible, and the high-NA tools are a blistering $400 million each, far more than the previous EUV rigs. And unlike those, the new machines are not a revolutionary leap upward. 

“This is like 30% to 50% better in terms of capability,” says Koch, the analyst and former ASML employee. “This is probably the first tool that hasn’t obviously made business sense right away for ASML.”

It’s not that the industry won’t eventually embrace high NA en masse, Koch says. Most companies will need to, if they want to keep going smaller. But TSMC is more likely to push ahead as far as it can go with its existing EUV tools, using onerous multi-patterning to wring as much as it can out of that generation until it absolutely needs to switch. 

“The industry has only shifted paradigms when it just absolutely cannot extend—even one more little bit—out of what it’s been doing,” Koch says. 


China isn’t the only party looking to upset the current balance of power. The dominance of ASML, and the swelling cost of its tools, is prompting other upstarts too. But instead of trying to replicate ASML’s breakthroughs in EUV, they’re doing an end run—working on lithography tools that use entirely different forms of light. These will be far cheaper, they promise, and just as powerful.

One is Substrate, a San Francisco–based startup. Founded four years ago, it’s working on a tool that uses x-ray light produced by a particle accelerator. X-rays have a remarkably tiny wavelength, making them a potentially powerful way to create minute features. 

Particle accelerators have historically been enormous, making them difficult to fit into a chipmaking process. Substrate says it has harnessed decades of scientific improvements in particle acceleration to produce a light source that’s smaller and suitable for mass production. 

Last year the company released images showing that it had created fine patterns, which Proud, the CEO, says are only possible now with a high-NA EUV machine. He says Substrate’s goal is to produce chips at scale by 2030. 

But Proud doesn’t intend to sell the tools to TSMC or Intel. Indeed, he doesn’t plan to sell them to anyone. Instead, Substrate wants to create its own fab, building chips using its own tools.  

“The amount of chips we’re going to need is going to be many orders of magnitude larger than even the wildest projections you have now.”

James Proud, cofounder and CEO, Substrate

The semiconductor industry, Proud argues, needs new approaches, because it’s become too pricey and too centralized. A single fab today can cost $25 billion to build, up from about $5 billion in the 2010s, the company notes. It’s driving the cost of a single wafer full of advanced chips up toward $100,000, Proud says. 

“That is, I think, a prohibitive cost,” he says. There also isn’t enough capacity in the supply chain: “It’s relatively slow and hard to flex to the current increase in demands.” He admires ASML’s EUV tooling—it’s “the apex implementation of that technology”—but new approaches are needed.

That’s partly for national security reasons. Proud and his team think it’s too dangerous for the US to rely on foreign supplies. But he also predicts the current AI boom will go into overdrive, creating a massive demand for chips that the existing ASML/TSMC duopoly won’t be able to deliver: “The amount of chips we’re going to need is going to be many orders of magnitude larger than even the wildest projections you have now.”

ASML’s machines use lasers and molten tin to generate the EUV light.
CHRISTOPHER PAYNE

Substrate predicts it will be able to produce finished wafers at $10,000 a pop—a tenth of where Proud predicts the rest of the industry is heading. Proud says that’s partly because the company’s system will be vertically integrated, so it will control all parts of the chipmaking process, but also because its lithography tooling will be less complex: “We’re able to put together in a sort of simpler package.”

Still, Substrate is playing its cards close to its chest. Unlike ASML, the company isn’t offering nuanced detail on how it generates light, or on how that then translates into making patterns on a wafer. 

Substrate’s ambitions give some industry observers pause. Hijink, who thinks it is probably “unachievable and impossible” to simultaneously master both a new form of lithography and high-throughput fab techniques, regards the company’s secrecy as a red flag. “This industry is about open innovation,” he says.

Koch is more impressed by its ambitions and funding. The type of technology it’s pursuing “is really cool,” he says. “It’s interesting.” But “there’s a long road between lab-scale demonstration and high volume,” he adds. “Is this like an imminent disruption to ASML? Probably not.”  

Another startup that is aiming to hit the market around the same time as Substrate is Lace Lithography. Based in Norway, it is devising an entirely different approach—one that doesn’t use light at all. Instead, an energized beam of helium atoms is pointed at the pattern on the reticle. When the helium atoms then hit the wafer, the atoms transfer their energy to it, imparting the design to the chip. 

The idea dates back a while. Bodil Holst, the CEO, took it up in 2008, when she was a physicist studying the use of atom beams. MIT professor Henry “Hank” Smith, a pioneer in using x-rays for lithography, told her she should explore using atoms as a mechanism for making microchips, because back then he wasn’t sure ASML’s EUV moonshot would work. “Even if it does, we’ll need atoms eventually,” he told her.

Holst did some experiments to investigate the idea further and partnered with a former PhD student—Adrià Salvador Palau, a physicist and expert in machine learning—to found Lace. Like Substrate’s, its tool is completely different from ASML’s massive machinery. The source of the excited atoms “looks a bit like a rocket motor,” says Palau. “It’s very cool.” While EUV’s wavelength is 13.5 nanometers, the helium atoms offer a precision of 0.1 nanometers. The process also requires far less power, and the machine is intended to be far smaller. Holst tells me the company aims to have machines ready to sell to fabs by 2029 or 2030.

“I think everybody’s really looking forward to something that extends a road map beyond light, beyond EUV,” Palau says. 

ASML is watching these upstarts with curiosity. Benschop says he can’t assess whether Substrate’s technology will work reliably and affordably, because the company hasn’t explained anything about its processes. But he went to a conference where Holst and Palau did a presentation outlining Lace Lithography’s technology.

“I’m incredibly impressed with how they do it,” he says. The problem, he says, is he doesn’t think the process produces patterns on the wafer that are deep enough to be useful. “I cannot see how they would scale it to a viable volume product,” he told me. 

He suspects ASML’s mastery of EUV will keep it on top for the near future. “So far, I have not seen a viable alternative,” he says. He thinks there’s “no serious runner-up” when it comes to volume manufacturing of the most advanced chip generations.

It’s true that major shifts in chipmaking are slow, says Chris Miller, a professor of international history at Tufts University and the author of Chip War, a book about the worldwide struggle for dominance in the industry. “No doubt we’ll eventually have alternatives [to EUV],” he told me via e-mail. “But it’s worth noting that lithography transitions have historically taken years, if not decades.” 


ASML’s executives, too, are pondering their future. Benschop expects high-NA technology to dominate chipmaking into the 2030s. Beyond that? The industry has, indeed, tended to shift to a new form of light every decade.

“You may argue it’s time for the next decade,” he told me after we’d stripped off our bunny suits and he was relaxing with a coffee. 

But ASML’s executives suspect they can continue to squeeze more capabilities out of EUV by increasing the numerical aperture even further on their existing machine. They’re already toying with a design that would take an NA of 0.55 to an NA of 0.75: “hyper NA.” It could let them pattern wafers with a resolution of six nanometers. They’re also working on standardizing their various optics into a platform of a single size, so customers could order one machine outfitted for either regular EUV, high NA, or hyper NA. If it’s all in the same-sized unit, it would simplify the costs and logistics of integrating each into a fab. If the company goes through with it, Benschop figures, the hyper-NA tool might hit the market seven or eight years from now and be sold in volume during the second half of the 2030s.

For now, the ball is in ASML’s court. “We’re pushing the limits of physics,” Pieters told me. The question now is whether anyone else can push harder. 

Clive Thompson is a science and technology journalist based in New York City. He wrote about the development of ASML’s original EUV machine in MIT Technology Review’s 2021 issue on computing.

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Comstock farms out minority interest in midstream subsidiary for $600 million

@import url(‘https://fonts.googleapis.com/css2?family=Inter:[email protected]&display=swap’); .ebm-page__main h1, .ebm-page__main h2, .ebm-page__main h3, .ebm-page__main h4, .ebm-page__main h5, .ebm-page__main h6 { font-family: Inter; } body { line-height: 150%; letter-spacing: 0.025em; } button, .ebm-button-wrapper { font-family: Inter; } .label-style { text-transform: uppercase; color: var(–color-grey); font-weight: 600; font-size: 0.75rem; } .caption-style { font-size: 0.75rem; opacity: .6; } #onetrust-pc-sdk [id*=btn-handler], #onetrust-pc-sdk [class*=btn-handler] { background-color: #c19a06 !important; border-color: #c19a06 !important; } #onetrust-policy a, #onetrust-pc-sdk a, #ot-pc-content a { color: #c19a06 !important; } #onetrust-consent-sdk #onetrust-pc-sdk .ot-active-menu { border-color: #c19a06 !important; } #onetrust-consent-sdk #onetrust-accept-btn-handler, #onetrust-banner-sdk #onetrust-reject-all-handler, #onetrust-consent-sdk #onetrust-pc-btn-handler.cookie-setting-link { background-color: #c19a06 !important; border-color: #c19a06 !important; } #onetrust-consent-sdk .onetrust-pc-btn-handler { color: #c19a06 !important; border-color: #c19a06 !important; } Comstock Resources Inc. sold a minority equity interest in its midstream subsidiary, Pinnacle Gas Services LLC, to certain funds managed by investment firm Sixth Street. Pinnacle provides gathering and treating services for Comstock’s Western Haynesville production through 246 miles of high-pressure pipeline and two gas treating plants. The infrastructure supports development of Comstock’s 540,000-net-acre Western Haynesville position, part of its 1,074,868 gross-acre (806,980 net) Haynesville/Bossier portfolio in Texas and Louisiana. Comstock is operating four rigs in the Western Haynesville this year as it continues delineating the play and expects to drill 21 wells and bring 20 online in 2026. The company also plans to operate five rigs in its legacy Haynesville position, where it expects to drill 50 wells and bring 48 online to support production growth through 2027. <!–> –><!–> –> Oct. 31, 2023 Sixth Street invested $600 million for a 27% equity interest in Pinnacle Gas Services, while Comstock Resources retains a 73% controlling interest and continues to manage and operate Pinnacle under a management services agreement. Under the terms of deal, Sixth Street’s ownership will be reduced to 19.5% when certain return thresholds are met, with Comstock’s interest increasing to 80.5%. Comstock chief

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Equinor aims to boost oil, gas production to 2.3 MMboe/d by 2030

Equinor ASA said it plans to increase oil and gas production to about 2.3 MMboe/d by 2030, supported by higher output from the Norwegian continental shelf (NCS) and international upstream growth.  The company, as part of its Capital Markets Day 2026, said it expects total production to rise by 150,000 boe/d by 2030, with NCS output increasing about 100,000 boe/d to 1.35 MMboe/d and international oil and gas production growing about 30% to roughly 950,000 boe/d. NCS-led upstream growth strategy Equinor described the NCS as the backbone of its upstream business and a key driver of long-term cash flow and value creation, with around 60% of capital expenditure directed to the basin. The operator plans to industrialize subsea field developments and increase recovery activity to accelerate resource maturation and reduce costs, targeting 6-8 new tieback projects per year toward 2035, noting the operating model shift aims to support a larger portfolio of subsea developments and increased recovery projects across the NCS. The NCS portfolio includes projects with break-even prices below US$35/bbl and payback times of less than 2.5 years. Continued increased recovery and exploration activity are expected to add new recoverable resources and extend field life, the company said. International oil and gas will account for about 30% of capital expenditure, with growth supported by assets in the United States, Brazil, Angola, the United Kingdom, and Canada. Across its international portfolio, production is expected to increase about 30% to roughly 950,000 boe/d by 2030. Total annual capex is guided to $11-13 billion in 2028-2030, following about $12 billion in 2027, including an additional $1 billion investment in high-return oil and gas projects that year.

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Edge networks a particular challenge for summer power, IT staffing needs

Power failures continue to dominate data center outage causes, accounting for 45% of impactful outages in Uptime Institute’s recently released 2026 Annual Outage Analysis report. While that figure declined from the previous year, it remains significantly higher than any other category. Within power-related incidents, UPS failures, transfer switch failures, and generator failures are the leading root causes. Uptime analysts said growing grid instability, power constraints, and high-density compute deployments are creating new pressure points for operators already running closer to capacity limits, according to a recent story on the report in Network World. Beyond power issues, hardware failures—particularly related to storage—also contribute to downtime. He noted that a lack of routine updates, especially to firmware, can make these problems worse, even when the underlying hardware is still functional.

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Turn enterprise AI into real business value with a secure, scalable factory

Building an enterprise AI factory is a complex endeavor that few organizations can tackle alone. The solution requires infrastructure capable of managing massive compute workloads generated by AI training and inferencing, high-capacity/low-latency networking within data centers and to the edge, and security to mitigate the risks that AI introduces. Abhinav Joshi, leader of AI solutions and product marketing at Cisco, identifies three key challenges inherent in building enterprise AI infrastructure: deployment complexity, security vulnerabilities, and performance bottlenecks. Agentic AI, with its heavy reliance on inferencing, places greater demands on infrastructure across all three dimensions. 3 challenges in building enterprise AI factories The deployment complexity challenge is driven by the need to quickly operationalize an AI infrastructure that fully integrates compute, networking, storage, security, and observability. A Kubernetes-based container management platform and a robust AI software toolchain are likewise essential to ensure the consistent development, testing, and deployment of containerized AI applications, Joshi says. The second challenge is mitigating security vulnerabilities. “Many organizations lack integrated security measures to protect the AI models, frameworks, applications, and the supporting infrastructure throughout the stack,” Joshi says. Attackers can exploit vulnerabilities by manipulating large language models (LLMs) with malicious inputs, which can disrupt operations and extract sensitive information. As AI agents ingest diverse data and act independently, they introduce new attack surfaces, including prompt injection, model poisoning, and data leaks.  Performance, especially around networking, is the third challenge. Tasks such as pre-training, post-training, and fine-tuning AI models, along with retrieval-augmented generation (RAG) pipelines and inferencing (including reasoning and agentic) all generate enormous amounts of network traffic. This creates severe bottlenecks across three critical communication paths: high-speed interconnects between graphics processing unit (GPU) servers, data throughput to storage layers, and real-time response delivery to end users. Without high-performance network connections, GPUs may be underutilized and jobs

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MSI’s Strategic Shift: From Server Vendor to Full-Spectrum AI Infrastructure Provider

The 100 kW rack figure places MSI’s offering squarely in the world of AI-era rack densities, where conventional air cooling becomes increasingly difficult or inefficient. The announcement also suggests that MSI is aligning with hyperscale and large cloud design principles, particularly through ORv3 and 48V power distribution. The company is moving from the “we have servers that can be liquid cooled” message, to “we can participate in rack-level AI infrastructure design.” The EIA air-cooled architecture, by contrast, is designed for more conventional data center environments. MSI says its 19-inch, 48RU EIA air-cooled rack supports standard deployments and can be configured with 16 2U2N multi-node systems, with AMD EPYC 9005 and Intel Xeon 6 platform options. That split matters because the AI infrastructure market is not moving in one uniform direction. Hyperscalers, neoclouds, and AI factories may move aggressively into ORv3, liquid cooling, busbar power, and rack-scale designs. Enterprise data centers, managed service providers, and colocation customers often need to work within existing 19-inch rack footprints and existing facility constraints. MSI wants to supply both markets. The CG681-S6093: MSI’s Flagship Liquid-Cooled AI Server The centerpiece of MSI’s NVIDIA-based AI server announcement is the CG681-S6093, a 6U liquid-cooled AI server based on NVIDIA MGX architecture. MSI says the system supports dual AMD EPYC processors and up to eight NVIDIA RTX PRO 6000 Blackwell Server Edition Liquid Cooled GPUs. It also supports 32 DDR5 DIMMs and NVIDIA ConnectX-8 SuperNICs with up to 8×400Gbps networking. This system is a direct entry into high-density AI inference, HPC, simulation, graphics, video, and physical AI workloads. The server is not positioned only for frontier model training. Instead, MSI appears to be aiming at the expanding middle of the AI infrastructure market: large inference clusters, visual computing, simulation, industrial AI, scientific computing, and agentic AI workloads. The next

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Cooling at AI Scale: Inside Motivair’s Blueprint for the Liquid-Cooled Data Center

BUFFALO, N.Y. — In the race to build AI infrastructure, the industry often focuses on GPUs, power availability, and the massive capital investments reshaping the digital infrastructure landscape. But a walk through Motivair’s manufacturing facility in Buffalo, as provided on the eve of the Motivair-Schneider Electric Global Press Event’s tour of the nearby Terawulf Lake Mariner AI campus, offers a reminder that another critical component of the AI boom is being built one coolant distribution unit at a time. During a recent Data Center Frontier Show podcast recorded at Motivair’s Buffalo headquarters, CEO Rich Whitmore described a reality that is becoming bedrock across the industry: Liquid cooling is now very far from being an emerging technology. It is now a prerequisite for deploying the most advanced AI systems. “You cannot deploy AI servers—at least the cutting-edge AI servers—without liquid cooling,” Whitmore said. That observation may be obvious to infrastructure veterans. Yet it points to a larger shift now underway across the data center ecosystem. As AI workloads drive rack densities beyond the practical limits of air cooling, thermal infrastructure has moved from a supporting role to a primary design consideration. For Whitmore and Motivair, that transition did not begin with ChatGPT. From Supercomputing to Commercial AI Long before AI became the defining growth story of the data center sector, Motivair was developing liquid cooling systems for high-performance computing and supercomputing environments. Whitmore describes today’s AI market as less of a technological revolution than a commercialization of capabilities that have existed for years inside elite computing environments. “We cut our teeth in high-performance computing and supercomputing,” Whitmore explained. “What we’re seeing today as we go into the AI era is really a commercialization of traditional supercomputing.” That experience has positioned Motivair differently than many newer entrants rushing into the liquid cooling

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From Components to AI Factories: Peter Panfil Says the Future of Data Centers Is All About Integration at Scale

ORLANDO, Fla. — For years, the data center industry optimized individual systems: power distribution, cooling, racks, UPS equipment, and mechanical infrastructure. In the AI era, according to Vertiv Distinguished Engineer and Vice President of Technical Business Development Peter Panfil, that approach is no longer sufficient. Speaking during Wednesday morning’s keynote at the 2026 7×24 Exchange Spring Conference, Panfil presented a vision in which the data center itself becomes a single, tightly orchestrated computing appliance—truly an “AI factory” whose success depends less on standalone components than on the seamless interaction between them. Throughout his presentation, titled “Scale at Speed: How Massively Parallel Compute GPUs Are Revolutionizing Data Center Design,” Panfil repeatedly returned to a single imperative: the AI infrastructure race is increasingly defined by execution velocity. “If you think you’re going big enough, go bigger,” he told attendees. “If you think you’re going fast enough, you’re going to have to go faster.” For an industry gathered under the conference’s overarching theme of future-proofing AI infrastructure, Panfil’s message suggested something subtly different. Rather than trying to predict the future, operators should build systems capable of adapting to it. “I would much rather be future ready,” he said, “than future proof.” Speed Becomes the New Competitive Metric One of the keynote’s recurring themes was that deployment speed has become an economic variable in its own right. Panfil argued that hyperscalers and AI providers increasingly view time-to-capacity as directly tied to business value, making delays in construction or commissioning far more expensive than traditional infrastructure inefficiencies. “The cost of speeding up has real benefits right now,” he observed. That urgency is changing the way facilities are assembled. Rather than coordinating numerous independent contractors and subsystem vendors on-site, Panfil described an emerging model built around highly standardized, factory-produced HAC [hot aisle containment] modules—or “hacks”—that arrive

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Beyond the GPU: Cisco Says AI’s Biggest Challenge May Be the Network That Connects It All

For much of the AI boom, the industry’s attention has centered on GPUs, power availability, and liquid cooling. But according to Cisco Senior Business Development Manager Robin Olds, another critical constraint is rapidly moving to the forefront: the network itself. Speaking with Data Center Frontier on the show floor at Fiber Connect 2026, Olds argued that AI represents a once-in-a-generation shift comparable to the birth of the commercial internet, fundamentally changing traffic patterns and forcing service providers, data center operators, hyperscalers, and emerging neoclouds to rethink infrastructure design. “It’s really like the internet when it was created,” Olds said. “We’re at another intersection in time where we could really see things happening.” AI Is Rewriting the Bandwidth Equation The most significant change may not be compute density alone but the sustained demand AI places on transport networks. According to Olds, service providers are already seeing AI traffic account for roughly 30% of utilization on backbone infrastructure; a dramatic increase from less than 1% only two years ago. As AI workloads continue to proliferate, those utilization levels are expected to rise further. The next wave of agentic AI could amplify that trend. Unlike consumer chatbots, which generate bursty request patterns, autonomous AI agents continuously interact with applications and external services, creating more persistent traffic flows. “Everything’s about chatbots,” Olds observed. “It’s very spiky—up, down. Agentic AI is going to maintain utilization because now I have agents working on my behalf.” For data center developers, network operators, and cloud providers alike, that implies planning not just for peak demand but for elevated baseline utilization across metro and long-haul infrastructure. Compressing the Network Stack Cisco’s response centers on architectural simplification. Olds highlighted the company’s Agile Services Networking framework, which combines router and optical networking technologies with coherent optics to converge functions that historically

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Microsoft will invest $80B in AI data centers in fiscal 2025

And Microsoft isn’t the only one that is ramping up its investments into AI-enabled data centers. Rival cloud service providers are all investing in either upgrading or opening new data centers to capture a larger chunk of business from developers and users of large language models (LLMs).  In a report published in October 2024, Bloomberg Intelligence estimated that demand for generative AI would push Microsoft, AWS, Google, Oracle, Meta, and Apple would between them devote $200 billion to capex in 2025, up from $110 billion in 2023. Microsoft is one of the biggest spenders, followed closely by Google and AWS, Bloomberg Intelligence said. Its estimate of Microsoft’s capital spending on AI, at $62.4 billion for calendar 2025, is lower than Smith’s claim that the company will invest $80 billion in the fiscal year to June 30, 2025. Both figures, though, are way higher than Microsoft’s 2020 capital expenditure of “just” $17.6 billion. The majority of the increased spending is tied to cloud services and the expansion of AI infrastructure needed to provide compute capacity for OpenAI workloads. Separately, last October Amazon CEO Andy Jassy said his company planned total capex spend of $75 billion in 2024 and even more in 2025, with much of it going to AWS, its cloud computing division.

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John Deere unveils more autonomous farm machines to address skill labor shortage

Join our daily and weekly newsletters for the latest updates and exclusive content on industry-leading AI coverage. Learn More Self-driving tractors might be the path to self-driving cars. John Deere has revealed a new line of autonomous machines and tech across agriculture, construction and commercial landscaping. The Moline, Illinois-based John Deere has been in business for 187 years, yet it’s been a regular as a non-tech company showing off technology at the big tech trade show in Las Vegas and is back at CES 2025 with more autonomous tractors and other vehicles. This is not something we usually cover, but John Deere has a lot of data that is interesting in the big picture of tech. The message from the company is that there aren’t enough skilled farm laborers to do the work that its customers need. It’s been a challenge for most of the last two decades, said Jahmy Hindman, CTO at John Deere, in a briefing. Much of the tech will come this fall and after that. He noted that the average farmer in the U.S. is over 58 and works 12 to 18 hours a day to grow food for us. And he said the American Farm Bureau Federation estimates there are roughly 2.4 million farm jobs that need to be filled annually; and the agricultural work force continues to shrink. (This is my hint to the anti-immigration crowd). John Deere’s autonomous 9RX Tractor. Farmers can oversee it using an app. While each of these industries experiences their own set of challenges, a commonality across all is skilled labor availability. In construction, about 80% percent of contractors struggle to find skilled labor. And in commercial landscaping, 86% of landscaping business owners can’t find labor to fill open positions, he said. “They have to figure out how to do

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2025 playbook for enterprise AI success, from agents to evals

Join our daily and weekly newsletters for the latest updates and exclusive content on industry-leading AI coverage. Learn More 2025 is poised to be a pivotal year for enterprise AI. The past year has seen rapid innovation, and this year will see the same. This has made it more critical than ever to revisit your AI strategy to stay competitive and create value for your customers. From scaling AI agents to optimizing costs, here are the five critical areas enterprises should prioritize for their AI strategy this year. 1. Agents: the next generation of automation AI agents are no longer theoretical. In 2025, they’re indispensable tools for enterprises looking to streamline operations and enhance customer interactions. Unlike traditional software, agents powered by large language models (LLMs) can make nuanced decisions, navigate complex multi-step tasks, and integrate seamlessly with tools and APIs. At the start of 2024, agents were not ready for prime time, making frustrating mistakes like hallucinating URLs. They started getting better as frontier large language models themselves improved. “Let me put it this way,” said Sam Witteveen, cofounder of Red Dragon, a company that develops agents for companies, and that recently reviewed the 48 agents it built last year. “Interestingly, the ones that we built at the start of the year, a lot of those worked way better at the end of the year just because the models got better.” Witteveen shared this in the video podcast we filmed to discuss these five big trends in detail. Models are getting better and hallucinating less, and they’re also being trained to do agentic tasks. Another feature that the model providers are researching is a way to use the LLM as a judge, and as models get cheaper (something we’ll cover below), companies can use three or more models to

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OpenAI’s red teaming innovations define new essentials for security leaders in the AI era

Join our daily and weekly newsletters for the latest updates and exclusive content on industry-leading AI coverage. Learn More OpenAI has taken a more aggressive approach to red teaming than its AI competitors, demonstrating its security teams’ advanced capabilities in two areas: multi-step reinforcement and external red teaming. OpenAI recently released two papers that set a new competitive standard for improving the quality, reliability and safety of AI models in these two techniques and more. The first paper, “OpenAI’s Approach to External Red Teaming for AI Models and Systems,” reports that specialized teams outside the company have proven effective in uncovering vulnerabilities that might otherwise have made it into a released model because in-house testing techniques may have missed them. In the second paper, “Diverse and Effective Red Teaming with Auto-Generated Rewards and Multi-Step Reinforcement Learning,” OpenAI introduces an automated framework that relies on iterative reinforcement learning to generate a broad spectrum of novel, wide-ranging attacks. Going all-in on red teaming pays practical, competitive dividends It’s encouraging to see competitive intensity in red teaming growing among AI companies. When Anthropic released its AI red team guidelines in June of last year, it joined AI providers including Google, Microsoft, Nvidia, OpenAI, and even the U.S.’s National Institute of Standards and Technology (NIST), which all had released red teaming frameworks. Investing heavily in red teaming yields tangible benefits for security leaders in any organization. OpenAI’s paper on external red teaming provides a detailed analysis of how the company strives to create specialized external teams that include cybersecurity and subject matter experts. The goal is to see if knowledgeable external teams can defeat models’ security perimeters and find gaps in their security, biases and controls that prompt-based testing couldn’t find. What makes OpenAI’s recent papers noteworthy is how well they define using human-in-the-middle

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